1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to arrangement of memory blocks and peripheral circuits thereof in a semiconductor memory device.
2. Description of the Background Art
In these years, semiconductor memory devices, particularly DRAMs (Dynamic Random Access Memories), are highly integrated with even larger capacity. With such increase in capacity, a memory cell array is divided into a great number of memory blocks (subarrays) because bit lines and word lines are divided into multiple bit lines and word lines to cope with increase in power consumption and delay time and decrease in signal voltage in a memory cell. Generally, since a semiconductor memory device has storage capacity of 2N bits which is the Nth power of 2, memory blocks are arranged in an even number of rows and columns.
FIGS. 16 and 17 show layouts of conventional DRAMs. These figures are shown in, for example, FIG. 1.14 in VLSI Memory by Kiyoo Ito, published by Baifukan Press, p. 19.
FIG. 16 shows an internal structure of a DRAM of 64 K bits. Referring to FIG. 16, the DRAM includes a semiconductor substrate 10, memory cell arrays MA1 and MA2 formed on semiconductor substrate 101 a row decoder 42 arranged to cross vertically over memory cell array MA1 or MA2, a column decoder 43 arranged to cross horizontally over memory cell array MA1 or MA2, a peripheral circuit 11 for memory cell array MA1, and a peripheral circuit 12 for memory cell array MA2.
FIG. 17 shows an internal structure of a DRAM of 64 M bits. Referring to FIG. 17, this DRAM includes semiconductor substrate 10, memory cell arrays MA1-MA4 formed on semiconductor substrate 10, row decoder 42 arranged to cross horizontally over memory cell array MA1-MA4, column decoder 43 arranged adjacent to one shorter side of each of memory cell arrays MA1-MA4, and a peripheral circuit 11 for memory cell arrays MA1-MA4.
Each of memory cell arrays MA1-MA4 shown in FIG. 17 is divided into 64 subarrays. FIG. 17 shows only subarrays SA1-SA64 in memory cell array MA3. Since this DRAM has storage capacity of 64 M bits, each of memory cell arrays MA1-MA4 includes 16M (16xc3x97220) memory cells, and each of subarrays SA1-SA64 includes 256 K (256xc3x97210) memory cells. Therefore, in this DRAM subarrays are arranged in 2 K rows and 128 columns.
Peripheral circuit 11 includes a control circuit (not shown) for controlling memory cell arrays MA1-MA4 and an input/output interface circuit (not shown). The input/output interface circuit is a circuit for converting an externally applied control signal and the write data to an internal signal to be supplied to the control circuit or outputting to outside the readout data transferred from memory cell arrays MA1-MA4 to the control circuit. The control circuit is a circuit for controlling memory cell arrays MA1-MA4 based on the data or the control signal applied to the input/output interface circuit.
Since a DRAM includes 2N memory cells, which is the Nth power of 2, it has been common to arrange subarrays in even number of rows and even number of columns. However, with an increase in capacity, the number of subarrays tends to grow increasingly. As a result, it is difficult to implement a DRAM of 1 G bit by the arrangement methods shown in FIGS. 16 and 17. More specifically, a memory cell array must be divided into multiple subarrays in a DRAM of 1 G bit, leading to unequal distances from the peripheral circuit to respective subarrays and to unequal signal delays.
One object of the present invention is to provide a semiconductor memory device having a large storage capacity.
Another object of the present invention is to provide a semiconductor memory device with equal signal delay.
Still another object of the present invention is to provide a novel method of arranging a plurality of memory blocks and a peripheral circuit thereof.
According to one aspect of the present invention, a semiconductor memory device includes a semiconductor substrate, a plurality of memory blocks, and a peripheral circuit therefor. The plurality of memory blocks are arranged on the semiconductor substrate to surround the center thereof. Each memory block includes a plurality of word lines, a plurality of bit lines crossing the word lines and a plurality of memory cells each corresponding to a crossing point of the word line and the bit line. The peripheral circuit is arranged on the semiconductor substrate at the center thereof.
According to another aspect of the present invention, a semiconductor memory device includes eight memory blocks and a peripheral circuit therefor. The eight memory blocks are arranged in three rows and three columns except for the second row of the second column. Each memory block includes a plurality of word lines, a plurality of bit lines crossing the word lines and a plurality of memory cells each corresponding to a crossing point of the word line and the bit line. The peripheral circuit is disposed at the second row of the second column.
According to still another aspect of the present invention, a semiconductor memory device includes four unit blocks. Each unit block includes eight memory blocks and a peripheral circuit therefor. Four unit blocks are arranged in two rows and two columns. Eight memory blocks are arranged in three rows and three columns except for the second row of the second column. Each memory block includes a plurality of word lines, a plurality of bit lines crossing the word lines and a plurality of memory cells each corresponding to a crossing point of the word line and the bit line. The peripheral circuit is disposed at the second row of the second column.
Therefore, according to the present invention, the distance from the peripheral circuit to each memory block is substantially equal, resulting in substantially equal signal delay. Consequently, a semiconductor memory device with a large storage capacity can be easily implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.